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| VORTEX86SX 32-BIT x86 Embedded SoC Brief Datasheet (v1.001) DMP Electronics INC www.VORTEX86SX.com VORTEX86SX 32-Bit x86 Embedded SoC CONTENTS 1 Overview ............................................................................3 2 Features .............................................................................3 3 Block Diagram ....................................................................4 3.1 3.2 3.3 System Block Diagram ..................................................................... 4 Functions Block Diagram ................................................................. 5 PCI Device List ............................................................................... 5 4 PIN Function List ...............................................................6 4.1 4.2 BGA Ball Map .................................................................................. 6 Signal Description ........................................................................... 7 5 Rreference Design Schematic .......................................... 22 6 Package Information ........................................................ 31 2 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC 1 Overview SPI (Serial Peripheral Interface), Fast Ethernet MAC, FIFO UART, USB2.0 Host and IDE controller into a System-on-Chip (SoC) design. Furthermore, this outstanding VORTEX86SX SoC can not only meet the requirements of embedded applications, such as Electronics Billboard, Firewall Router, Industrial Single-Board-Computers, Receipt Printer Controller, Thin Client PC, Auto Vehicle Locator, Finger Print Identification, Web Camera Thin Server, RS232-to-TCP Transmitter. but also can meet the critical temperature demand, spanning from -40 to +85 . VORTEX86SX is the x86 SoC (System on Chip) with 0.13 micron process and ultra low power consumption design (less than 1 watt). This comprehensive SoC has been integrated with rich features, such as various I/O (RS-232, Parallel, USB and GPIO), BIOS, WatchDog Timer, Power Management, MTBF counter, LoC (LAN on Chip),JTAG etc., into a 27x27 mm, 581-pin BGA packing single chip. The VORTEX86SX is compatible with Win CE, Linux and DOS. It integrates 32KB write through direct map L1 cache, 16-bit ISA bus, PCI Rev. 2.1 32-bit bus interface at 33 MHz, SDRAM, DDR2, ROM controller, IPC (Internal Peripheral Controllers with DMA and interrupt timer/counter included), 2 - - Features x86 Processor Core 6 stage pipe-line Embedded I/D Separated L1 Cache 16K I-Cache, 16K D-Cache - - - - - - - - - - - - SDRAM/DDRII Control Interface - 16 bits data bus - Support DLL for clock phase auto-adjustion - SDRAM support up to 133MHz - SDRAM support up to 128Mbytes - DDRII support up to 166MHz - DDRII support up to 256Mbytes IDE Controller - Support 2 channels Ultra-DMA 100 (Disk x 4) bits; 1, 1.5 or 2 stop bits; even, odd or no parity; 5~8 data bits Support TXD_En Signal on COM1/COM2 Port 80h output data could be sent to COM1 by software programming Parallel Port x 1 Support SPP/EPP/ECP mode General Chip Selector 2 sets extended Chip Selector I/O-map or Memory-map could be configurable I/O Addressing: From 2 byte to 64K byte Memory Address: From 512 byte to 4G Byte General Programmable I/O Supports 40 dedicated programmable I/O pins Each GPIO pin can be individually configured to be an input/output pin LPC (Low Pin Count) Bus Interface - Support 2 programable registers to decode LPC address MAC Controller x 1 PCI Control Interface - USB 2.0 Host Support Supports HS, FS and LS 4 port - - - - Up to 3 sets PCI master device 3.3V I/O PS/2 Keyboard and Mouse Interface Support Compatible with 8042 controller ISA Bus Interface AT clock programmable 8/16 Bit ISA device with Zero-Wait-State Generate refresh signals to ISA interface during DRAM refresh cycle - - Redundant System Support Speaker out Embedded 256KB Flash For BIOS storage The Flash could be disable & use external Flash ROM DMA Controller Interrupt Controller Counter/Timers - - - - - - - 2 sets of 8254 timer controller Timer output is 5V tolerance I/O on 2nd Timer JTAG Interface supported for S.W. debugging Input clock - - - - - - - - 14.318MHz 32.768KHz Output clock 24 MHz 25 MHz MTBF Counter Real Time Clock Below 2uA power comsuption on Internal Mode (Estimation Value) Operating Voltage Range Core voltage: 1.2 V ~ 1.4V I/O voltage: 1.8V 5% , 3.3 V 10 % FIFO UART Port x 5 (5 sets COM Port) Compatible with 16C550/16C552 Default internal pull-up Supports the programmable baud rate generator with the data rate from 50 to 460.8K bps The character options are programmable for 1 start Operating temperature -40 ~ 85 Package Type 27x27mm, 581 ball BGA VORTEX86SX Brief Datasheet Version 1.001 3 VORTEX86SX 32-Bit x86 Embedded SoC 3 Block Diagram 3.1 System Block Diagram 4 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC 3.2 Function Block Diagram (Internal) 3.3 PCI Device List Device# IDSEL Function 0 Function 1 0 AD11 NB 1 AD12 PCI SLOT1 2 AD13 PCI SLOT2 3 AD14 PCI SLOT3 4 AD15 PCI SLOT4 5 6 7 AD18 SB 8 AD19 MAC 9 10 AD21 USB0 OHCI USB0 EHCI 11 AD22 USB1 OHCI USB1 EHCI 12 AD23 IDE 13 VORTEX86SX Brief Datasheet Version 1.001 5 VORTEX86SX 32-Bit x86 Embedded SoC PCI_Interface A 26 AD24 DP1 DP0 TRDY_ AD10 AD5 AD1 DP3 REXT0 PCIRST_ AD13 AD3 TXP RXP DP2 B C D E F G H J ETHERNET K L M N P TOP VIEW USB_Interface R T U REXT1 GPIO_Interface V RTC_Xin W AVDD3 Y AA AB AC AD AE AF DCD2_/PWM0CLK DSR2_/PWM0GATE XOUT_14.318 POWER_GOOD CLK25MOUT CTS2_/PWM1GATE DM2 AVSSPLL1 RTC_Xout AVSS3 26 25 AD25 CBE_3 AD2 DM0 IRDY_ AD14 DM1 STOP_ AD9 AD7 TXN AVSSPLL0 AD4 RXN DM3 XIN_14.318 MTBF RTS2_/PWM1OUT SIN2/PWM2CLK CLK24MOut DTR2_/PWM2OUT TXD_EN2/PWM2GATE AVDD1 AVSS2 AVDD33_1 AVDDPLL1 SERIRQ 25 24 AD26 CBE_2 DEVSEL_ AD15 PAR AVSS0 AVDD33_0 CBE_0 VCCA0 VCCA1 FRAME_ AD0 ISET VSSA1 Vss_pll_1 Vdd_pll_1 Vdd_pll_0 DCD1_/GPIO_40 RI2_/PWM1CLK Vss_pll_0 SOUT2/PWM0OUT AVDD2 LAD0 LAD1 LAD2 LAD3 24 23 AD27 AD16 CBE_1 AD12 AD6 Duplex Link/Active VSSABG INTA_ VSSA0 AD17 AD11 VCCAPLL TEST0 VCC_SPI VCCABG AVDDPLL0 TEST4 VSSAPLL AVSS1 SPEAKER Vdd_core Vss_io Vdd_io CTS1_/GPIO_47 DTR1_/GPIO_45 DSR1_/GPIO_46 RTC_IRQ8_/GPIO_34 RTC_RD_GPIO_36 RTC_PS 23 22 AD28 AD18 AD19 TEST2 TEST1 ATSTP AVDD0 E_SPI_DI/GPIOP_33 SYSFAILOut_ Ext_Switch_fail Vdd_core E_SPI_CLK/GPIOP_31 Vss_io Vdd_io RTS1_/GPIO_42 RI1_/GPIO_43 SOUT1/GPIO_41 22 21 AD29 AD20 GND_SPI AD8 ROM_CS_ TEST3 TXEN0 RXDV0 RXC0 AD21 TXC0 ATSTN RTC_AS_GPIO_37 VBat E_SPI_CS/GPIOP_30 Vdd_core VBatGnd RTC_WR_GPIO_35ExtSysFailIn_ EXT_GPCS_ E_SPI_DO/GPIOP_32 Vss_io Vdd_io TXD_EN1 SIN1/GPIO_44 GPIO_P2_1/SA25 21 20 PCICLK_2 AD31 AD23 INTC_ AD22 AD30 LPC_Interface GPIO_P2_7/SA31 GPIO_P2_6/SA30 Vss_io GPIO_P2_4/SA28 GPIO_P2_2/SA26 GPIO_P2_5/SA29 20 19 PCICLK_0 PREQ2 INTB_ VCC3V TXD0_3 TXD0_0 PGNT0 PGNT2 INTD_ GPIO_P1_7 GPIO_P2_0/SA24 RXD0_0 RXD0_3 Vdd_io Vss_io Vss_io Vss_core LFRAME_ LDRQ_ GPIO_P1_6 GPIO_P1_5 GPIO_P1_4 GPIO_P1_0 19 18 PCICLK_1 PREQ1 PREQ0 VCC3V PGNT1 GPIO_P0_7 GPIO_P1_3 GPIO_P1_2 GPIO_P23/SA27 GPIO_P0_5 GPIO_P0_3 18 RXD0_1 RXD0_2 Vdd_io Vss_io Vss_io Vss_core Vss_io Vss_io 17 MD4 MD0 MD14 DQM1 GNDK GND_R3 TXD0_2 TXD0_1 GPIO_P0_6 GPIO_P1_1 GPIO_P0_1 GPIO_P0_0 GPIO_P0_4 GPIO_P0_2 17 MDIO COL0 VCC3V GND_R3 Vdd_io Vss_io Vss_core Vss_core KBDATA/A20GATE_ 16 MD3 MD1 MD15 MD9 DQS1 GND_R3 MDC SD3 IOR_ GPCS0_ GPCS1_ SD15 SD14 16 VCC3V VCC3V VCC3V VCC3V GND_R3 Vdd_io Vss_io Vss_io Vss_core MSDATA 15 MD2 MD8 MD7 MD11 MD12 GND_R3 LA20 LA18 LA23 LA19 DRQ7 SD12 15 MD13 IS A _Interface 14 MD5 DQM0 DQS0 VCCK MD10 RAM_Interface VCCK VCCK VCCK VCCK GND_R3 VCC3V Vdd_io Vss_io Vss_core MSCLK Vss_core KBCLK_KBRST_ GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 VCC3V GNDK Vdd_io Vss_io SD4 IRQ9 SD2 SD6 LA21 SD11 14 13 MD6 WE_ BA2 BA0 CAS_ RAS_ VCCK CS_1 CS_0 IOCHCK_ SA2 SBHE_ LA22 SA5 DACK_2 13 GNDK GNDK GND_R3 GND_R3 VCC3V GNDK GNDK GNDK Vss_io Vdd_core Vss_core Vss_core 12 MA10 MA6 BA1 SA3 DRQ0 Vss_core SD8 MEMW_ SA1 12 MA13 GNDK GND_R3 VCC3V Vss_io Vdd_core Vss_core Vss_core 11 MA1 MA5 MA9 MA7 MA11 DRQ5 SA4 Vss_core DACK_6 SD10 DRQ6 11 MA12 GNDK GNDK GNDK GNDK GND_R3 VCC3V Vdd_io VCCK Vss_io Vdd_core Vdd_core 10 MA0 MA3 MA4 VDLL0 GNDDLL0 SMEMR_ DACK_5 Vss_core SD13 SD9 SYSCLK 10 GNDDLL1 MA8 TMS GNDK GNDK GNDK VCCK Vdd_io Vss_io Vss_io Vss_io 9 MA2 SDRAMCLKN SDRAMCLKP VDLL1 SA19 SA17 DRQ2 DACK_0 LA17 MEMR_ 9 VCCO GNDK VCCK 8 7 VCCO SMEMW_ AEN IRQ12 0WS_ IOCHRDY_ OSC14M 8 IDE_Interface/COM Port VCCO GNDK GNDO TCK VCCO GNDO GNDO GNDO TDO TDI SOUT9 SIN9 PE/SDD9 SOUT4 SIN4 CTS4_/SIOW_ DCD4_/SA2 DSR4_/SCS1_ RTS4_/SINT PD5/SDD5 BUSY/SDD10 SLCT/SDD8 VCCO GNDO GNDO GNDO GNDO GNDPLL0 GNDPLL1 PD6/SDD6 DTR4_/SA0 Vss_io PDD12 SD0 SA10 SA8 IRQ5 IRQ7 DACK_7 7 PIN Function List 6 SD7 Vdd_io Vss_core Vdd_core SA7 IRQ10 REFRESH_ 6 PDD2 PDD1 PDD11 RI4/SA1 Vss_io BGA Ball Map 5 4 3 2 1 A B DRQ3 Vdd_io Vss_core Vdd_core SA18 SA9 TC 5 VCCO VCCO VCCO GNDO VCCK VPLL0 VPLL1 PD7/SDD7 ACK_/SDD11 PD4/SDD4 ERR_/SDD14 PDD10 PDD5 PDD6 PDD7 Vss_core Vdd_io SD5 Vdd_io Vss_core Vdd_core DRQ1 BALE IRQ15 4 N2S S2N SIN3 RTS3_/SRST_ TESTCLK PD3/SDD3 CTS3_/SIOR_ PD0/SDD0 DCD3_/SDRQ GNTx_ REQx_ SOUT3 DSR3_/SCBLID_ DTR3_/SDACK_ INIT_/SDD13 RI3/SIORDY PA2 AFD_/SDD15 SLIN_/SDD12 PDD9 PIORDY PD2/SDD2 PD1/SDD1 PIOW_ PDD0 PDD8 Vdd_io Vdd_io DACK_3 SA16 DACK_1 SA0 SA11 IOCS16_ IRQ11 3 PINT PA1 PA0 PCS1_ PDD4 PDD15 PDD14 IOW_ SA12 SA14 SA6 SA13 IRQ3 IRQ14 2 STB_/SCS0_ PRST_ PDD3 PDD13 PDRQ PDACK_ PCBLID_ PIOR_ PCS0_ SD1 SA15 RSET_DRV IRQ6 IRQ4 MEMCS16_ 1 C D E F G H J K L M N P R T U V W Y AA AB AC AD AE AF 4 4.1 Pin #1 Corner 6 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC 4.2 Signal Description This chapter provides a detailed description of VORTEX86SX signals. A signal with the symbol "_n" at the end of itself indicates that this pin is low active. Otherwise, it is high active. The following notations are used to describe the signal types: I O OD I/O Input pin Output pin Output pin with open-drain Bi-directional Input/Output pin System (7 PINs) PIN No. AA26 AB26 Y26 Y25 AA25 AB25 Y23 Symbol PWRGOOD 25MOUT XOUT_14.318 XIN_14.318 MTBF CLK24MOUT SPEAKER Type I O O I O O Description Power-Good Input. This signal comes from Power Good of the power supply to indicate that the power is available. The VORTEX86SX uses this signal to generate reset sequence for the system. 25MHz Clock output. Crystal-out. Frequency output from the inverting amplifier (oscillator). Crystal-in. 14.318MHz frequency input, within 100 ppm tolerance, to the amplifier (oscillator). MTBF Flag output. 24MHz Clock output Speaker Output. This pin is used to control the Speaker Output and should be connected to the Speaker SDRAM /DDRII Interface (44 PINs) PIN No. B9 A9 D13 E12 C13 Symbol SDRAMCLK SDRAMCLKN RAS_ CAS_ WE_ Type O O O O O Description Clock output. This pin provides the fundamental timing for the SDRAM /DDR controller. Clock output. This pin provides the fundamental timing for the SDRAM /DDR controller. Row Address Strobe. When asserted, this signal latches row address on positive edge of the SDRAM/DDR clock. This signal also allows row access and pre-charge. Column Address Strobe. When asserted, this signal latches column address on the positive edge of the SDRAM/DDR clock. This signal also allows column access and pre-charge. Memory Write Enable. This pin is used as a write enable for the memory data bus. Chip Select CS[1:0]. These two pins activate the SDRAM devices. First Bank of SDRAM accepts any command when the CS0_n pin is active low. Second Bank of SDRAM accepts any command when the CS1_n pin is active low. For DDRII, only CS0_n activates the DDR device. Data Mask DQM[1:0]. These pins act as synchronized output enables during read cycles and byte masks during write cycles. Data Strobe DQS[1:0 for DDR only. Output with write data, input with the read data for source synchronous operation. B13, E13 CS_[1:0] O B14, D17 E16, D14 DQM[1:0] DQS[1:0] O I/O VORTEX86SX Brief Datasheet Version 1.001 7 VORTEX86SX 32-Bit x86 Embedded SoC Bank Address BA[1:0]. These pins are connected to SDRAM/DDR as bank address pins. Strap[17:16]. Memory Select, Default pull high. Strap[17] F12, D12 BA[1:0]/Strap[17:16] O 0 0 1 C12 D16, C17, C14, D15, C15, E14, C16, E15, B15, A13, A14, A17, A16, A15, B16, B17 A10 BA[2] O Strap[16] 0 1 0 DRAM Select SDRAM Reserved DDR 1 1 DDRII (Default) Bank Address [2]. These pins are connected to SDRAM/DDR as bank address pins. Memory Data MD[15:0]. These pins are connected to the SDRAM/DDR data bus. Memory Address MA[0]. Normally, these pins are used as the row and column address for SDRAM/DDR. Memory Address MA[1]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[1]. Pull it high to enable GPIO2. Default pull high. Pull it low to enable Address[31:24]. Memory Address MA[2]. Normally, these pins are used as the row and column address for SDRAM/DDR. Memory Address MA[3]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[3]. PLL_TEST_OUT_EN_, Default pull low. Pull it high to enable PLL_TEST_OUT_EN_. Pull it low to disable PLL_TEST_OUT_EN_. Memory Address MA[4]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[4]/[10]. SDRAM/DDR clock, Default pull high. Strap[10] Strap[4] 0 1 0 SDRAM clock 100MHz 133MHz (Internal default) 166MHz MD[15:0] I/O MA[0] O A11 MA[1]/Strap[1] O C9 MA[2] O B10 MA[3] /Strap[3] O C10 MA[4] /Strap[4] O 0 0 1 C11,B12,B11 MA[7:5]/Strap[7:5] I/O F9 MA[8]/Strap[8] I/O 1 1 200MHz Memory Address MA[7:5]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[7:5] / CPU Clock 3b'000 / Bypass mode 3b'001 / SYN_DISABLE_ (CPU clock same to SDRAM Clock) 3b'010 / 233MHz 3b'011 / 266MHz 3b'100 / 300MHz (Internal default) 3b'101 / 333MHz 3b'110 / 366MHz 3b'111 / 400MHz Memory Address MA[8]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[8]. Pull it high to enable VORTEX86SX JTAG. Default internal pull-high. 8 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC Memory Address MA[9]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[9]. Pulled low: 33 PINS is for IDE2. Pulled high: 33 PINS is for COM3/4 and Parallel Port. Default internal pull-high. Memory Address MA[10]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[4]/[10]. SDRAM/DDR clock, Default pull low. Strap[10] A12 MA[10]/Strap[10] I/O 0 0 1 Strap[4] 0 1 0 Memory clock 100MHz 133MHz (Internal default) 166MHz D11 MA[9]/Strap[9] I/O E11 MA[11]/Strap[11] I/O F11,F10 MA[13:12]/ Strap[13:12] I/O 1 1 200MHz Memory Address MA[11]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[11]. Pulled low is Internal RTC. Default internal pull-low. Pulled high is External RTC Memory Address MA[13:12]. Normally, these pins are used as the row and column address for SDRAM/DDR. Strap[13:12]. 00 : flash-8bits 01 : flash-16bits 11 : Internal SPI. Default internal pull-high. USB 0, 1, 2, 3 (10 PINs) PIN No. N26 N25 M26 M25 T26 T25 R26 R25 P26 U26 Symbol USB0_DP USB0_DM USB1_DP USB1_DM USB2_DP USB2_DM USB3_DP USB3_DM REXT[0]: REXT[1]: Type I/O Description Universal Serial Bus Controller 0 Port 0. These are the serial data pair for USB Port 0. 15k pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 0 Port 1. These are the serial data pair for USB Port 1. 15k pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 1 Port 0. These are the serial data pair for USB Port 2. 15k pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 1 Port 1. These are the serial data pair for USB Port 3. 15k pull down resistors are connected to DP and DM internally. Universal Serial Bus Controller 0 External Reference Resistance. 510 10% Universal Serial Bus Controller 1 External Reference Resistance. 510 10% I/O I/O I/O I I PCI Bus Interface (56 PINs) PIN No. B19, B18, C18 D19, D18 ,C19 D26 A19 A18 A20 Symbol PREQ_[2:0] PGNT_[2:0] PCIRST_ PCICLK_0 PCICLK_1 PCICLK_2 Type I O O O Description PCI Bus Request. These signals are the PCI bus request signals used as inputs by the internal PCI arbiter. PCI Bus Grant. These signals are the PCI bus grant output signals generated by the internal PCI arbiter. PCI Reset. This pin is used to reset PCI devices. When it is asserted low, all the PCI devices will be reset. PCI Clock Output. This clock is used by all of the VORTEX86SX logic that is in the PCI clock domain. VORTEX86SX Brief Datasheet Version 1.001 9 VORTEX86SX 32-Bit x86 Embedded SoC C20, B20, A21 A22, A23, A24, A25, B26, D20, E20, C21, B21, C22, B22, C23, B23, E24, E25, E26, H22, G23, F26, F25, H21, G25, J22, G26, H25, H26, J25, J26, H24 B25, B24, G22, F24 C24 C25 AD[31:0] I/O PCI Address and Data. The standard PCI address and data lines. The address is driven with PCI Frame assertion and data is driven or received in the following clocks. CBE_[3:0] FRAME_ IRDY_ I/O I/O I/O C26 D24 D25 G24 H23 F19 F20 E19 TRDY_ DEVSEL_ STOP_ PAR INTA_ INTB_ INTC_ INTD_ I/O I/O I/O I/O I I I I Bus Command and Byte Enables. During the address phase, C/BE_n[3:0] define the Bus Command. During the data phase, C/BE[3:0]_n define the Byte Enables. PCI Frame. This pin is driven by a PCI master to indicate the beginning and duration of a PCI transaction. PCI Initiator Ready. This pin is asserted low by the master to indicate that it is able to transfer the current data transfer. A data was transferred if both IRDY_n and TRDY_n are asserted low during the rising edge of the PCI clock. PCI Target Ready. This pin is asserted low by the target to indicate that it is able to receive the current data transfer. A data was transferred if both IRDY_n and TRDY_n are asserted low during the rising edge of the PCI clock. Device Select. This pin is driven by the devices which have decoded the addresses belonging to them. PCI Stop. This pin is asserted low by the target to indicate that it is unable to receive the current data transfer. PCI Parity. This pin is driven to even parity by PCI master over the AD[31:0] and C/BE_n[3:0] bus during address and write data phases. It should be pulled high through a weak external pull-up resistor. The target drives parity during data read. PCI INTA_. PCI interrupt input A. It connects to PCI INTA_n when normal modes of PCI Interrupts are supported. PCI INTB_. PCI interrupt input B. It connects to PCI INTB_n when normal modes of PCI Interrupts are supported. PCI INTC_. PCI interrupt input C. It connects to PCI INTC_n when normal modes of PCI Interrupts are supported. PCI INTD_. PCI interrupt input D. It connects to PCI INTD_n when normal modes of PCI Interrupts are supported. EXTERNAL SPI/PORT[3-0] Interface (4 PINs) PIN No. W21 W22 Y21 Y22 Symbol E_SPI_CS_/GPIO_P3[0] E_SPI_CLK/GPIO_P3[1] E_SPI_DO/GPIO_P3[2] E_SPI_DI/GPIO_P3[3] Type I/O I/O I/O I/O Description External SPI Chip Select General-Purpose Input/Output P3[0] External SPI Clock General-Purpose Input/Output P3[1] External SPI Data Ouput General-Purpose Input/Output P3[2] External SPI Data Input General-Purpose Input/Output P3[3] ISA Bus Interface ( 87 PINs) PIN No. AA13 AE16, AF16, AD10, AF15, AF14, AE11, AE10, AD12,Y6, AD14, Y4, AA14, 10 Symbol IOCHCK_ SD[15:0] Type I I/O Description I/O Channel Check. Provides the system board with parity (error) information about memory or devices on the I/O channel. ISA high and low byte slot data bus. These are the system data lines. These signals read data and vectors into CPU during memory or I/O read cycles or interrupt acknowledge cycles and outputs data from CPU during VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC AA16, AC14, Y1, AA7 memory or I/O write cycles. IOCHRDY_ AEN I O ISA system ready. This input signal is used to extend the ISA command width for the CPU and DMA cycles. ISA address enable. This active high output indicates that the system address is enabled during the DMA refresh cycles. ISA slot address bus. These signals are high impedance during hold acknowledge. ISA slot address bus. ISA slot address bus for 62-pin slot. ISA Bus high enable. In master cycle, it is an input polarity signal and is driven by the master device. ISA latched address bus. These are input signal during ISA master cycle. ISA memory read. This signal is an input during ISA master cycle. ISA memory write. This signal is an input during ISA master cycle. Driver Reset. This output signal is driven active during system power up. AE8 AB8 AA3, AA1, AB2, AD2,AA2, AD3, AB7, AE5, AC7, AD6, AC2, AE13, AB11, AA12, AB13 AF12, AC3 SA[16:0] O AA9, AD5, AB9 AC13 AC15, AD13, AE14, AA15, AD15, AB15, AE9 SA[19:17] SBHE_ LA[23:17] MEMR_ MEMW_ RST_DRV IRQ[7:3], IRQ[12:9], IRQ[15:14] DRQ[7:5], DRQ[3:0] 0WS_ SMEMR_ SMEMW_ IOW_ IOR_ DACK_[7:5], DACK_[3:0] REFRESH_ SYSCLK TC BALE MEMCS16_ IOCS16_ OSC14M O O O O O O AF9 AE12 AF4, AF2, AC8, AF3, AE6, AB14, AE7, AC1, AD7, AD1, AE2 AE15, AF11, AA11, Y5, AC9, AD4, AB12 I Interrupt request signals. These are interrupt request input signals. I I O O O O O O O O O I I O DMA device request. These are DMA request input signals. ISA zero wait state. This is the ISA device zero-wait state indicator signal. This signal terminates the CPU ISA command immediately. ISA system memory read. This signal indicates that the memory read cycle is for an address below 1M byte address. ISA system memory write. This signal indicates that the memory write cycle is for an address below 1M byte address. ISA I/O write. This signal is an input during ISA master cycle. ISA I/O read. This signal is an input during ISA master cycle. DMA device acknowledge signals. These are DMA acknowledge demultiplex select signals. Input function is for hardware setting. Refresh cycle indicator. ISA master uses this signal to notify DRAM needs refresh. During the memory controller's self-acting refresh cycle, M6117D drives this signal to the I/O channels. System Clock Output. This signal clocks the ISA bus. DMA end of process. This is the DMA channel terminal count indicating signal. Bus address latch enable. BALE indicates the presence of a valid address at I/O slots. ISA 16-bit memory device select indicator signal. ISA 16-bit I/O device select indicator signal. 14.318MHz clock out AD8 AA10 AA8 Y2 AB16 AF7, AD11, AB10, Y3, AF13, AB3, AD9 AF6 AF10 AF5 AE4 AE1 AE3 AF8 Chip Selection Interface (3 PINs) PIN No. AC16 AD16 G21 Symbol GPCS0_ GPCS1_ ROMCS_/SPICS_ Type O O O Description ISA Bus Chip Select 0. This pin is the chip select for ISA bus. ISA Bus Chip Select 1. This pin is the chip select for ISA bus. ROM Chip Select. This pin is used as a ROM chip select. SPI Chip Select. This pin is used as SPI flash chip select. VORTEX86SX Brief Datasheet Version 1.001 11 VORTEX86SX 32-Bit x86 Embedded SoC Redundant (4 PIN) PIN No. U21 U22 V22 V21 Symbol EXTSYSFAILIN_ SYSFAILOUT_ EXT_SWITCH_FAIL_ EXT_GPCS_ Type I O I I Description External system fail input. This pin is the system fail in for redundant. System fail output. This pin is the system fail out for redundant. External switch fail. This pin is the switch input for redundant. External GPCS input. This pin is the GPCS in for redundant. KBD/MOUSE Interface (4 PINs) PIN No. Symbol KBCLK/KBRST KBDAT/A20GATE MSCLK MSDAT Type I/O I/O I/O I/O Description Keyboard Clock. This pin is keyboard clock when used internal 8042. Keyboard Reset. This pin is Keyboard reset when used external 8042. Keyboard Data. This pin is keyboard data when used internal 8042. Address Bit 20 Mask. This pin is A20 mask when used external 8042. Mouse Clock. This pin is mouse clock when used internal 8042. Mouse Data. This pin is mouse data when used internal 8042. V13 V16 V14 V15 RTC/PORT3[7-4] Interface (7 PINs) PIN No. N21 Symbol RTC_AS /GPIO_P3[7] RTC_RD_ /GPIO_P3[6] RTC_WR_ /GPIO_P3[5] RTC_IRQ8_ /GPIO_P3[4] RTC_PS RTC_XOUT RTC_XIN Type I/O Description RTC Address Strobe. This pin is used as the RTC Address Strobe and should be connected to the RTC. General-Purpose Input/Output GPIO P3[7]. I/O RTC Read Command. This pin is used as the RTC Read Command and should be connected to the RTC. General-Purpose Input/Output GPIO P3[6]. I/O RTC Write Command. This pin is used as the RTC Write Command and should be connected to the RTC. General-Purpose Input/Output GPIO P3[5]. I/O I O I RTC Interrupt Input. This pin is used as the RTC Interrupt input. General-Purpose Input/Output GPIO P3[4]. RTC Battery Power Sense. Crystal-out. Crystal-in. P22 T21 R22 T22 V25 V26 COM1/PORT4 Interface (9 PINs) PIN No. AE21 AE22 Symbol SIN1/GPIO_P4[4] SOUT1/GPIO_P4[1] Type I/O General-Purpose Input/Output GPIO port4 [4]. Transmit Data. FIFO UART transmitter serial data output from the serial port. I/O General-Purpose Input/Output GPIO port4 [1]. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. General-Purpose Input/Output GPIO port4 [2]. Description Receive Data. FIFO UART receiver serial data input signal. AF22 RTS1/GPIO_P4[2] I/O 12 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. General-Purpose Input/Output GPIO port4 [7]. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. General-Purpose Input/Output GPIO port4 [6]. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. General-Purpose Input/Output GPIO port4 [0]. Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. General-Purpose Input/Output GPIO port4 [3]. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. General-Purpose Input/Output GPIO port4 [5]. COM1 TX Status. This pin will be high when COM1 is trnamitting. AE23 CTS1/GPIO_P4[7] I/O AF23 DSR1/GPIO_P4[6] I/O AF24 DCD1/GPIO_P4[0] I/O AD22 RI1/GPIO_P4[3] I/O AD23 DTR1/GPIO_P4[5] I/O AD21 TXD_EN1 I/O VORTEX86SX Brief Datasheet Version 1.001 13 VORTEX86SX 32-Bit x86 Embedded SoC COM2/PWM Interface (9 PINs) PIN No. AF25 Symbol SIN2/PWM2CLK Type I Description COM2 Receive Data. FIFO UART receiver serial data input signal. PWM Timer2 Clock. This pin is PWM timer2 external clock input when SB register C0h bit2 is 1 (PINs for PWM). COM2 Transmit Data. FIFO UART transmitter serial data output from the serial port. PWM Timer0 Output. This pin is PWM timer0 output when SB register C0h bit2 is 1 (PINs for PWM). Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. PWM Timer1 Output. This pin is PWM timer1 output when SB register C0h bit2 is 1 (PINs for PWM). Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. PWM Timer1 Gate. This pin is PWM timer1 gate mask when SB register C0h bit2 is 1 (PINs for PWM). Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. PWM Timer0 Gate. This pin is PWM timer0 gate mask when SB register C0h bit2 is 1 (PINs for PWM). Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. PWM Timer0 Clock. This pin is PWM timer0 external clock input when SB register C0h bit2 is 1 (PINs for PWM). AE24 SOUT2/PWM0OUT O AD25 RTS2/PWM1OUT O AD26 CTS2/PWM1GATE I AE26 DSR2/PWM0GATE I AC26 DCD2/PWM0CLK I 14 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. PWM Timer1 Clock. This pin is PWM timer1 external clock input when SB register C0h bit2 is 1 (PINs for PWM). Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. PWM Timer1 Output. This pin is PWM timer1 output when SB register C0h bit2 is 1 (PINs for PWM). COM2 TX Status. This pin will be high when COM2 is trnamitting. AE25 TXD_EN2/PWM2GATE I/O PWM Timer2 Gate. This pin is PWM timer2 gate mask when SB register C0h bit2 is 1 (PINs for PWM). AD24 RI2/PWM1CLK I AC25 DTR2/PWM2OUT O COM3, 4, 9 (6 PIN) PIN No. G3 G2 N6 M6 K6 J6 Symbol SIN3 SOUT3 SIN4 SOUT4 SIN9 SOUT9 Type I O I O I O Description COM3 Receive Data. FIFO UART receiver serial data input signal. COM3 Transmit Data. FIFO UART transmitter serial data output from the serial port. COM4 Receive Data. FIFO UART receiver serial data input signal. COM4 Transmit Data. FIFO UART transmitter serial data output from the serial port. COM9 Receive Data. FIFO UART receiver serial data input signal. COM9 Transmit Data. FIFO UART transmitter serial data output from the serial port. IDE 0, 1/COM3,4,PRINT1 Interface (58 PINs) PIN No. K4, K5, L5, M4, K3, M2, L2, K2 Symbol PD[7:0]/SDD[7:0] Type I/O Description Parallel port data bus bit . Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. SLCT. An active high input on this pin indicates that the printer is selected. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. PE. An active high input on this pin indicates that the printer has detected the end of the paper. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. BUSY. An active high input indicates that the printer is not ready to receive data. Refer to the description of the parallel port for definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. N5 SLCT/SDD8 I/O L6 PE/SDD9 I/O M5 BUSY/SDD10 I/O VORTEX86SX Brief Datasheet Version 1.001 15 VORTEX86SX 32-Bit x86 Embedded SoC ACK_. An active low input on this pin indicates that the printer has received data and is ready to accept more data. Refer to the description of the parallel port for the definition of this pin in ECP and EPP mode. L4 ACK_/SDD11 I/O M3 SLIN_/SDD12 J1 INIT_/SDD13 N4 ERR_/SDD14 IDE Secondary Channel Data Bus. SLIN_. Output line for detection of printer selection. Refer to the description of SLIN_: OD the parallel port for the definition of this pin in ECP and EPP mode. SDD12: I/O IDE Secondary Channel Data Bus. INIT_. Output line for the printer initialization. Refer to the description of the INIT_: OD parallel port for the definition of this pin in ECP and EPP mode. SDD13: I/O IDE Secondary Channel Data Bus. ERR_. An active low input on this pin indicates that the printer has encountered an error condition. Refer to the description of the parallel port for I/O the definition of this pin in ECP and EPP mode. IDE Secondary Channel Data Bus. AFD_. An active low output from this pin causes the printer to auto feed a line after a line is printed. Refer to the description of the parallel AFD_: OD port for the definition of this pin in ECP and EPP mode. SDD15: I/O IDE Secondary Channel Data Bus. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. IDE Secondary Channel Reset. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. IDE Secondary Channel DMA Request. Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. IDE Secondary Channel IO Write Strobe. Clear to Send. This active low input for the primary and secondary serial ports. A handshake signal notifies the UART that the modem is ready to receive data. The CPU can monitor the status of the CTS_n signal by reading bit 4 of Modem Status Register (MSR). A CTS_n signal states the change from low to high after the last MSR read sets bit 0 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when CTS_n changes the state. The CTS_n signal has no effect on the transmitter. Note: Bit 4 of the MSR is the complement of CTS_n. IDE Secondary Channel IO Read Strobe. L3 AFD_/SDD15 H3 RTS3_/SRST_ O J2 DCD3_/SDRQ I P6 CTS4_/SIOW_ I/O H2 CTS3_/SIOR_ I/O 16 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. IDE Secondary Channel IO Channel Ready. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. IDE Secondary Channel DMA Acknowledge. Request to Send. Active low Request to Send output for UART port. A handshake output signal notifies the modem that the UART is ready to transmit data. This signal can be programmed by writing to bit 1 of Modem Control Register (MCR). The hardware reset will clear the RTS_n signal to be inactive mode (high). It is forced to be inactive during the loop-mode operation. IDE Secondary Channel Interrupt. Ring Indicator. This active low input is for the UART ports. A handshake signal notifies the UART that the telephone ring signal is detected by the modem. The CPU can monitor the status of the RI_n signal by reading bit 6 of the Modem Status Register (MSR). An RI_n signal states the change from low to high after the last MSR read sets bit 2 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when RI_n changes state. Note: Bit 6 of the MSR is the complement of RI_n. IDE Secondary Channel Device Address. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. IDE Secondary Channel Cable Assembly Type Identifier. Data Terminal Ready. This is an active low output for the UART port. A handshake output signal signifies the modem that the UART is ready to establish data communication link. This signal can be programmed by writing to bit 0 of Modem Control Register (MCR). The hardware reset will clear the DTR_n signal to be inactive during the loop-mode operation. IDE Secondary Channel Device Address. Data Carrier Detect. This active low input is for the UART ports. A handshake signal notifies the UART that the carrier signal is detected by the modem. The CPU can monitor the status of the DCD_n signal by reading bit 7 of the Modem Status Register (MSR). A DCD_n signal states the change from low to high after the last MSR read sets bit 3 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DCDJ changes state. Note: Bit 7 of the MSR is the complement of DCD_n. IDE Secondary Channel Device Address. G1 RI3/SIORDY I F1 DTR3_/SDACK_ O U6 RTS4_/SINT I/O V5 RI4/SA1 I/O H1 DSR3_/SCBLID_ I V6 DTR4_/SA0 O R6 DCD4_/SA2 I VORTEX86SX Brief Datasheet Version 1.001 17 VORTEX86SX 32-Bit x86 Embedded SoC STB_. An active low output is used to latch the parallel data into the printer. Refer to the description of the parallel port for the definition of this pin in ECP STB_: OD and EPP mode. SCC_0: I IDE Secondary Channel Chip Select. Data Set Ready. This active low input is for the UART ports. A handshake signal notifies the UART that the modem is ready to establish the communication link. The CPU can monitor the status of the DSR_n signal by reading bit5 of the Modem Status Register (MSR). A DSR_n signal states the change from low to high after the last MSR read sets bit1 of the MSR to a "1". If bit 3 of the Interrupt Enable Register is set, the interrupt is generated when DSR_n changes state. Note: Bit 5 of the MSR is the complement of DSR_n. IDE Secondary Channel Chip Select. M1 V2, W2, P1, P5, U5, P4, N3, U3, U4 T4, R4, U2, N1, R5, T5, T3 R1 R3 V1 P3 T1 N2 K1, P2, R2 U1 W1 T2 PRST_ O IDE Primary Channel Reset. L1 STB_/SCS_0 T6 DSR4_/SCS1_ I PDD[15:0] I/O IDE Primary Channel Data Bus. PDRQ PIOW_ PIOR_ PIORDY PDACK_ PINT PA[2:0] PCBLID_ PCS0_ PCS1_ I O O I O I O I O O IDE Primary Channel DMA Request. IDE Primary Channel IO Write Strobe. IDE Primary Channel IO Read Strobe. IDE Primary Channel IO Channel Ready. IDE Primary Channel DMA Acknowledge. IDE Primary Channel Interrupt. IDE Primary Channel Device Address IDE Primary Channel Cable Assembly Type Identifier. IDE Primary Channel Chip Select. IDE Primary Channel Chip Select. LPC Bus Interface (7 PINs) PIN No. W24 W23, V23, U23, T23 U18 V18 Symbol SERIRQ LAD[3:0] LFRAME_ LDRQ_ Type I/O I/O O I Description Serial Interrupt Request. This pin is used to support the serial interrupt protocol of common architecture. LPC Command, Address and Data LAD[3:0]. These pins are used to be command/address/data pins of Low-Pin-Count Function. Low Pin Count FRAME_n Signal. This signal is used as a frame signal of low pin count protocol.. Low Pin Count DMA Request Signal. This signal is used as a DMA request signal of low pin count protocol. 18 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC GPIO Interface (24 PINs) PIN No. AA18, AA17, AE18, AE17, AF18, AF17, AC17, AD17, AA19, AC19, AD19, AE19, AB18, AC18, AB17, AF19 Symbol GPIO_P0[7:0] GPIO_P1[7:0] Type Description General-Purpose Input/Output P0[7-0] and P1[7-0]. Those pins can be programmed input or output individually. General-Purpose Input/Output P2[7-0] . Those pins can be programmed input or output individually. Address[31:24]. I/O AA20, AB20, AD20, GPIO_P2[7:0]/Addre AE20, AD18, AF20, ss[31:24] AF21, AB19 I/O Ethernet Interface (24 PINs) PIN No. L22 K22 J24 F22 F21 K25 K26 L25 L26 J16 K16 L16 M21 M18, M17, L17, L18 L21 J21 J18, J17, K17, K18 K21 Symbol Link/Active Duplex ISET ATSTP ATSTN TXN TXP RXN RXP MDC MDIO COL0 RXC0 RXD0_[3:0] RXDV0 TXC0 TXD0_[3:0] TXEN0 O I/O I I I I I O O Type Description Link/Active: Link/active status Duplex: Duplex status ISET: External resistor connecting pin for BIAS ATSTP: VGA and ADC testing pin for input and output (positive) ATSTN: VGA and ADC testing pin for input and output (negative) TXN: 10B-T/100BT transmitting output pin/ reveiving input pin (positive) TXP: 10B-T/100BT transmitting output pin/ reveiving input pin (negative) RXN: 10B-T/100BT reveiving input pin/ transmitting output pin (positive) RXP: 10B-T/100BT reveiving input pin/ transmitting output pin (negative) MDC: MII management data clock is sourced by the VORTEX86SX to the external PHY devices as a timing reference for the transfer of information on the MDIO signal. MDIO: MII management data input/output transfers control information and status between the external PHY and the VORTEX86SX. COL0: This pin functions as the collision detection. When the external physical layer protocol (PHY) device detects a collision, it asserts this pin. RXC0: Supports the receive clock supplied by the external PMD device. This clock should always be active. RXD0_[3:0]: Four parallel receiving data lines. This data is driven by an external PHY attached to the media and should be synchronized with the RXC signal. RXDV0: Data valid is asserted by an external PHY when the received data is present on the RXD[3:0] lines and is de-asserted at the end of the packet. This signal should be synchronized with the RXC signal. TXC0: Supports the transmit clock supplied by the external PMD device. This clock should always be active. TXD0_[3:0]: Four parallel transmit data lines. This data is synchronized to the assertion of the TXC signal and is latched by the external PHY on the rising edge of the TXC signal. TXEN0: This pin functions as Transmit Enable. It indicates that a transmission to an external PHY device is active on the MII port. JTAG Interface (4 PINs) PIN No. G6 J9 G7 H6 Symbol TDO TMS TCK TDI Type O I I I Description TDO: JTAG Test Data Output pin. TMS: JTAG Test Mode Select pin. TCK: JTAG Test Clock Input pin. TDI: JTAG Test Data Input pin. VORTEX86SX Brief Datasheet Version 1.001 19 VORTEX86SX 32-Bit x86 Embedded SoC TEST PIN (10 PIN) PIN No. J3 E23, E21, D22, E22, D23, F2, F3, E2, E3 Symbol TESTCLK TEST[8:0] Type I/O I/O For Testing used For Testing used. Test 3 and Test 4 must pull high to 3.3V. Description 1.2V POWER (14 PINs) PIN No. D9, D10 E9, E10 F8,F13,F14,G4, J14,K14,L14,N9 ,M14,P9 E7,E8,E17,J10, J11,J12,K9, K10,K11,K12, L9,L10,L11, L12,M9,M10, M11 Symbol VDDLL (2 PINs) GNDDLL (2 PINs) VCCK (10 PINs) Type I I I DLL power DLL ground Core power Description GNDK (17 PINs) I Code ground 1.8V POWER (57 PINs) PIN No. C4,C5,C6,C7, D4,D7,D8,E4 D5,D6,E5,E6, F4,F5,F6,F7, G5 AA21,AA22, AA23,AC4, AC5,AC6,T11, T12,U10,V10 T16, T17, T18, U11, U12, U13, U14, U15, U16, V4, V11, V12, AB4, AB5, AB6, AC10, AC1, AC12 Symbol VCCO (8 PINs) GNDO (9 PINs) Type I I Description SDR/DDRII power (3.3V/1.8V) SDR/DDRII gound Vdd_core (10 PINs) I Core power Vss_core (18 PINs) I Core ground N22, R24, R23, W26 N24, P23, T24, W25 V24, N23 U25, P25 AVDD[3:0] AVSS[3:0] AVDDPLL[1:0] AVSSPLL[1:0] I I I I Analog power Analog gound USB PLL power USB PLL ground Battery POWER (2 PIN) PIN No. P21 R21 Symbol VBat VBatGnd Type I I Battery power for RTC Battery gound for RTC Description 20 VORTEX86SX Brief Datasheet Version 1.001 VORTEX86SX 32-Bit x86 Embedded SoC 3.3V Power (87 PINs) PIN No. H4, J4 H5, J5 AA24, AB24 Y24, AC24 E18, F18, J15, K15, L15, M15, M16, P10, P11, P12, P13, P14 F15, F16, F17, J13, K13, L13, M12, M13, N10, N11, N12, N13, N14, N15, N16 AA4, AA5, AA6, AC21, AC22, AC23, N17, N18, P15, P16, R9, R10, R13, R14, V3, W3, W4 P17, P18, R11, R12, R15, R16, R17, R18,T9, T10, T13, T14, T15, U9, U17, V9, V17, W5, W6, AB21, AB22, AB23, AC20 Symbol VPLL (2 PINs) GNDPLL (2 PINs) Vdd_pll (2 PINs) Vss_pll (2 PINs) VCC3V (12 PINs) Type I I I I I Analog power Analog gound Analog power Analog gound Analog power Description GND_R3 (15 PINs) I Analog gound Vdd_io (17 PINs) I IO power Vss_io (23 PINs) I IO gound K23 J23 M22 M23 K24 L23 L24 M24 P24 U24 F23 D21 VSSAPLL VCCAPLL VSSABG VCCABG VCCA0 VSSA0 VCCA1 VSSA1 AVDD33_0 AVDD33_1 VCC_SPI GND_SPI (2 PINs) I I I I I I I I I I I I Analog ground Analog power Analog gound Analog power Analog power Analog gound Analog power Analog gound Analog power Analog power SPI flash power SPI flash ground VORTEX86SX Brief Datasheet Version 1.001 21 5 4 3 2 1 ISA BUS PCI BUS SA[0..19] D D 8 SA[0..19] SD[0..15] SD[0..15] 8 U1B AD[0..31] VORTEX86SX 8 PREQ0 PREQ1 PREQ2 PGNT0 PGNT1 PGNT2 PREQ-0 PREQ-0 C18 B18 B19 C19 D18 D19 F24 G22 B24 B25 CBE0 CBE1 CBE2 CBE3 PCICLK0 PCICLK1 A20 LA17 LA18 LA19 LA20 LA21 LA22 LA23 8 8 8 8 8 8 8 8 8 8 INT-A INT-B INT-C INT-D FRAMEIRDYTRDYDEVSELSTOPPAR 8 8 8 8 8 8 8 8 PCIRSTPCIRSTFRAMEIRDYTRDYDEVSELSTOPPAR INT-A INT-B INT-C INT-D D26 C24 C25 C26 D24 D25 G24 H23 F19 F20 E19 PCICLK2 -PCIRST -FRAME -IRDY -TRDY -DEVSEL -STOP PAR -INTA -INTB -INTC -INTD A19 8 PCICLK1 PCICLK1 R21 22 PCICLK1R A18 U1C VORTEX86SX AD[0..31] 8 8 PGNT-0 PGNT-0 C SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 SA0 SA1 SA2 SA3 SA4 SA5 SA6 SA7 SA8 SA9 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 8 8 8 8 CBE-0 CBE-1 CBE-2 CBE-3 CBE-0 CBE-1 CBE-2 CBE-3 LA17 LA18 LA19 LA20 LA21 LA22 LA23 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 GPCS0 GPCS1 TP1 4 4 8 8 8 8 8 8 8 8 8 8 8 8 8 8 DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 GPCS0 GPCS1 AD00 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 H24 J26 J25 H26 H25 G26 J22 G25 H21 F25 F26 G23 H22 E26 E25 E24 B23 C23 B22 C22 B21 C21 E20 D20 B26 A25 A24 A23 A22 A21 B20 C20 AA7 Y1 AC14 AA16 AA14 Y4 AD14 Y6 AD12 AE10 AE11 AF14 AF15 AD10 AF16 AE16 SD00 SD01 SD02 SD03 SD04 SD05 SD06 SD07 SD08 SD09 SD10 SD11 SD12 SD13 SD14 SD15 8 8 8 8 8 8 8 8 8 8 8 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 IRQ3 IRQ4 IRQ5 IRQ6 IRQ7 IRQ9 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 AE2 AD1 AD7 AC1 AE7 AB14 AE6 AF3 AC8 AF2 AF4 SA00 SA01 SA02 SA03 SA04 SA05 SA06 SA07 SA08 SA09 SA10 SA11 SA12 SA13 SA14 SA15 SA16 SA17 SA18 SA19 AC3 AF12 AB13 AA12 AB11 AE13 AC2 AD6 AC7 AE5 AB7 AD3 AA2 AD2 AB2 AA1 AA3 AB9 AD5 AA9 C IRQ03 IRQ04 IRQ05 IRQ06 IRQ07 IRQ09 IRQ10 IRQ11 IRQ12 IRQ14 IRQ15 LA17 LA18 LA19 LA20 LA21 LA22 LA23 AE9 AB15 AD15 AA15 AE14 AD13 AC15 DRQ0 DRQ1 DRQ2 DRQ3 DRQ5 DRQ6 DRQ7 AB12 AD4 AC9 Y5 AA11 AF11 AE15 AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AD27 AD28 AD29 AD30 AD31 B 8 8 8 8 8 8 8 8 8 8 8 8 IOCHRDY IOCHCK AEN SBHE MEMR MEMW RSTDRV OWS SMEMR SMEMW IOW IOR IOCHRDY AE8 IOCHCK AA13 AEN AB8 SBHE AC13 MEMR AF9 MEMW AE12 RSTDRV AB1 OWS AD8 SMEMR AA10 SMEMW AA8 IOW Y2 IOR AB16 -IOCHRDY -IOCHCK AEN -SBHE -MEMR -MEMW RSET_DRV -0WS -SMEMR -SMEMW -IOW -IOR 8 8 8 8 8 8 8 REFRESH MEMCS16 IOCS16 OSC BALE TC SYSCLK REFRESH AF6 MEMCS16 AE1 IOCS16 AE3 R22 22 AF8 BALE AE4 TC AF5 R23 22 AF10 DACK0 DACK1 DACK2 DACK3 DACK5 DACK6 DACK7 AD9 AB3 AF13 Y3 AB10 AD11 AF7 B -REFRESH -MEMCS16 -IOCS16 OSC14M BALE TC SYSCLK -GPCS0 -GPCS1 -ROMCS AC16 AD16 G21 A A DMP ELECTRONICS INC. Title VORTEX86SX PCI/ISA BUS Size Date: 4 3 2 Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 Sheet 1 Rev 1.1 2 of 8 5 5 4 3 2 1 VORTEX86SX F1 VCC L1 USBD1+ USBD11 4 SF2012900YSB LUSBD1LUSBD1+ L2 LUSBD23 USBD2+ UL-1 L3 USBD02 4 F2 AVDD1 USBD34 2 SF2012900YSB AVDD3 1 LUSBD3+ LUSBD2LUSBD2+ 3 USBD3+ LUSBD3J2 LUSBD3LUSBD3+ L4 3 SF2012900YSB LUSBD0+ LP-ISM110 0805 VCC 1 AVDD0 USBD0+ LUSBD0GGND GGND 4 LUSBD2+ 1 2 SF2012900YSB USBD2LUSBD0LUSBD0+ USBD1+ USB1A1 LUSBD12 LUSBD1+ 3 USBD1USBD0+ USBD0LP-ISM110 0805 U1F TXD+ TXD- K26 K25 TXP TXN DP0 DM0 T26 T25 LAN USBx4 USBD2+ USBD2USBD3+ USBD3510 510 RXIN+ RXIN- L26 L25 RXP RXN DP1 DM1 R26 R25 D LINK/ACTIVE L22 DUPLEX K22 R24 6.19K 1% J24 U5 U6 U7 U8 H3 H4 VCC -DATA +DATA GND HOLE HOLE VCC -DATA +DATA GND HOLE HOLE U1 U2 U3 U4 H5 H6 Link/Active Duplex ISET DP2 DM2 N26 N25 F22 F21 ATSTP ATSTN DP3 DM3 M26 M25 USBx2 D K16 J16 MDIO MDC REXT0 REXT1 U26 R25 P26 R26 CLK25MOUT AB26 K21 J21 K18 K17 J17 J18 AVDD0 W26 TXEN0 TXC0 TXD00 TXD01 TXD02 TXD03 AVSS0 W25 AVDD1 R23 AVSS1 T24 L16 M21 L21 L18 L17 M17 M18 AVDD2 R24 COL0 RXC0 RXDV0 RXD00 RXD01 RXD02 RXD03 AVSS2 P23 C VCCAPLL J23 VCCAPLL AVDD3 N22 1 3 5 7 9 2 4 6 8 10 HEADER 5X2/BOX USBx2 C K23 AVDDPLL0 VSSAPLL AVSS3 N24 GGND GGND VCCABG M23 VCCABG AVDDPLL0 V24 M22 AVDDPLL1 VSSABG AVSSPLL0 U25 VCC VCCA0 K24 VCCA0 AVDDPLL1 N23 L23 AVDD33 VSSA0 AVSSPLL1 P25 LAN TX/RX LINK U3 RXIN+ RXIN6 8 7 TXD3 2 TXD+ 1 R29 50 104 103 C13 C14 104 104 C15 104 C16 104 75 75 75 75 R30 50 R31 50 R32 TS6121A C11 C12 50 R33 R34 R35 R36 RD+ RDCT TDCT TD+ RX+ CT RXTXCMT TX+ 11 10 9 14 15 16 ARX+ CCT ARXATXCCMT ATX+ L1 L2 L7 L8 TD+ TDNC NC UL-2 L3 RO+ L6 L5 L4 RONC NC DUPLEX LINK/ACTIVE R27 R28 1K 1K L24 VCCA1 AVDD33_0 U24 M24 VSSA1 AVDD33_1 P24 USB1B1 L10 L12 PLED0 PLED1 VCC VCC L9 L11 B B L5 VCC1.8 C5 104 103 C6 BEAD VCCAPLL L7 BEAD VCC3 VCC1.8 L6 BEAD AVDD0 AVDDPLL0 RJ45 C1 C2 C3 C4 104 103 104 103 L8 VCC1.8 BEAD VCCABG L10 BEAD VCC3 VCC1.8 L9 BEAD AVDD1 AVDDPLL1 HOLE HOLE H1 H2 C7 C8 C9 C10 104 103 104 103 C17 102/3KV GGND A L11 VCC3 C22 104 103 C23 BEAD VCCA0 L13 BEAD VCC3 VCC1.8 L12 BEAD AVDD3 AVDD33 C18 C19 C20 C21 104 103 104 103 A DMP ELECTRONICS INC. Title VORTEX86SX LAN/USB Size Date: 4 3 2 Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 Sheet 1 Rev 1.1 3 of 8 5 5 4 3 2 1 VORTEX86SX VCC3 R37 RN19 10Kx4 J3 8 6 4 2 -RST J4 1 2 VCC GND G C25 104 HEADER 2 V 1K R PWRGD U4 MAX809S 1K R38 VCC3 VCC3 U1G POWER GOOD PWRGD AA26 POWER_GOOD 7 5 3 1 KBCLK KBDATA MSCLK MSDATA V13 V16 V14 V15 -LFRAME -LDRQ SERIRQ U18 V18 W24 KBCLK/-KBRST KBDATA/-A20GATE MSCLK MSDATA LPC BUS C24 10pF HEADER 5-1.25mm TCK TDO TDI TMS 1 2 3 4 5 D RXD9\ TXD9\ K6 J6 SIN9 SOUT9 LAD0 LAD1 LAD2 LAD3 T23 U23 V23 W23 D PWRGD 6 SYS-FAIL-IN SYS-FAIL-OUT SYS-SW-IN SYS-GPCS-IN U21 U22 V22 V21 CLK24MOut AB25 JTAG -ExtSysFailIn -SYSFAILOut Ext_Switch_fail EXT_GPCS MTBF-OUT AA25 TDO TDI TCK TMS G6 H6 G7 J9 TDO TDI TCK TMS JTAG MTBF SPEAKER Y23 TESTCLK J3 SPEAKER C26 22pF XX1 Y25 XIN_14318 R39 2 Y1 14.318MHz TEST0 TEST1 TEST2 TEST3 TEST4 D23 E22 D22 E21 E23 VCC3 1 C27 1M 22pF XX2 Y26 Vdd_pll_0 AB24 VDDPLL0 XOUT_14318 C28 22pF XY1 V26 Vss_pll_0 AC24 RTC_Xin 2 R40 VCC J6 SYS-FAIL-OUT TXD9\ 2 2 HEADER 5X2-2.0mm GPCS0 GPCS1 GPCS0 GPCS1 1 3 5 7 9 2 4 6 8 10 4.7K Y2 Vdd_pll_1 AA24 REDUNDANCY KBD/MOUSE C C 32.768KHz Vss_pll_1 Y24 J5 13 F3 VCC VCC LP-ISM110 0805 14 1 C29 1M 22pF XY2 V25 VPLL0 H4 VPLL0 RTC_Xout VBAT RXD9\ R41 SYS-FAIL-IN SYS-GPCS-IN SYS-SW-IN GNDPLL0 H5 VCC3 D1 A P21 VBat VPLL1 J4 D2 A R42 C FM160 C 1N4148 GNDPLL1 J5 1 2 3 4 5 6 1 3 5 7 KBD 15 C30 VDLL1 D9 VDLL0 330 104 GNDDLL1 E9 + BT1 VDLL0 D10 2 4 6 8 CR2354 R21 F2 E2 E3 F3 RN20 10Kx4 VBatGnd -REQx -GNTx N2S S2N GNDDLL0 E10 - KBDATA KBCLK L14 L15 BEAD BEAD B SPEAKER SP1 R43 22 MSDATA MSCLK C31 47pF BUZZER C32 47pF C33 47pF L16 L17 C34 47pF BEAD BEAD B 16 Q1 C35 3904 104 VCC SPEAKER R44 4.7K L18 BEAD VDDPLL0 VCC3 MOUSE 17 PS/2 KB/MS GGND C36 C37 7 8 9 10 11 12 104 103 L19 BEAD VPLL0 VCC3 C38 C39 POWER LED LED2 C LED-SMD A R45 1K VCC 104 103 A A VCC1.2 L20 BEAD VDLL0 DMP ELECTRONICS INC. C40 C41 104 103 MTBF-OUT MTBF LED LED3 C LED-SMD A R46 1K VCC Title VORTEX86SX KBD/MS/LPC/JTAG Size Date: Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 3 2 Rev 1.1 Sheet 1 4 of 8 5 4 5 4 3 2 1 U1E VORTEX86SX VBAT RS232 RS485 RI1 DTR1 CTS1 TXD1 RTS1 COM1 J45A1 -E_SPI_CS/GPIO30 E_SPI_CLK/GPIO31 E_SPI_DO/GPIO32 E_SPI_DI/GPIO33 R47 J7 U5 RXD1 VCC VCC DSR1 U6 RXD1_B TXDEN1 1-RS485+ 1-RS485TXD1\ DCD1 ADM483 1 2 3 4 DO DO_E DI_E DI VCC DA+ DBGND 8 6 7 5 HEADER 3 C42 1uF CTS1\ TXD1\ DTR1\ RI1\ RXD1_A RXD1\ RXD1_B 1 2 3 RS232/RS485 SEL 1-2:COM1 RS232 2-3:RS485 1K DCD1\ RTS1\ DSR1\ RXD1_A RI1 DTR1 CTS1 TXD1 RTS1 RXD1 DSR1 DCD1 L21 L22 L23 L24 L25 L26 L27 L28 BEAD BEAD BEAD BEAD BEAD BEAD BEAD BEAD W21 W22 Y21 Y22 SPICS SPICLK SPIDO SPIDI D GP00 GP01 GP02 GP03 GP04 GP05 GP06 GP07 AD17 AC17 AF17 AF18 AE17 AE18 AA17 AA18 GPIO_P00 GPIO_P01 GPIO_P02 GPIO_P03 GPIO_P04 GPIO_P05 GPIO_P06 GPIO_P07 RTC_IRQ8/GPIO34 -RTC_WR/GPIO35 -RTC_RD/GPIO36 RTC_AS/GPIO37 RTC_PS R22 T21 P22 N21 T22 GP34 GP35 GP36 GP37 5 9 4 8 3 7 2 6 1 DCON9MX2 D H1 H2 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 AF19 AB17 AC18 AB18 AE19 AD19 AC19 AA19 GPIO_P10 GPIO_P11 GPIO_P12 GPIO_P13 GPIO_P14 GPIO_P15 GPIO_P16 GPIO_P17 -DCD1/GPIO40 SOUT1/GPIO41 -RTS1/GPIO42 -RI1/GPIO43 SIN1/GPIO44 -DTR1/GPIO45 -DSR1/GPIO46 -CTS1/GPIO47 TXD_EN1 VCC AF24 AE22 AF22 AD22 AE21 AD23 AF23 AE23 AD21 DCD1\ TXD1\ RTS1\ RI1\ RXD1\ DTR1\ DSR1\ CTS1\ TXDEN1 GGND RS485-1 J8 1-RS485+ 1-RS485- GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 C43 MAX213 104 VCC 104 104 104 C44 C45 C46 AB19 AF21 AF20 AD18 AE20 AD20 AB20 AA20 GPIO_P20/SA24 GPIO_P21/SA25 GPIO_P22/SA26 GPIO_P23/SA27 GPIO_P24/SA28 GPIO_P25/SA29 GPIO_P26/SA30 GPIO_P27/SA31 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 HEADER 3-2.54mm/BOX C C -DCD2/PWM0CLK SOUT2/PWM0OUT -RTS2/PWM1OUT -RI2/PWM1CLK SIN2/PWM2CLK DTR2_/PWM2OUT -DSR2/PWM0GATE -CTS2/PWM1GATE TXD_EN2/PWM2GATE AC26 AE24 AD25 AD24 AF25 AC25 AE26 AD26 AE25 DCD2\ TXD2\ RTS2\ RI2\ RXD2\ DTR2\ DSR2\ CTS2\ TXDEN2 GPIO PORT 0/1 RI2 DTR2 CTS2 TXD2 RTS2 DCD2\ RTS2\ DSR2\ RXD2_A RS232 RS485 VCC COM2 J45B1 J9 J10 U7 RXD2 VCC DSR2 U8 RXD2_B TXDEN2 DCD2 TXD2\ 1 2 3 4 RXD2_A RXD2\ RXD2_B 1 2 3 B GP00 GP01 GP02 GP03 GP04 GP05 GP06 GP07 CTS2\ TXD2\ DTR2\ RI2\ 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 GP10 GP11 GP12 GP13 GP14 GP15 GP16 GP17 RS232/RS485 SEL 1-2:COM2 RS232 2-3:RS485 HEADER 3 VCC 8 6 7 5 DO DO_E DI_E DI ADM483 VCC DA+ DBGND 2-RS485+ 2-RS485- RI2 DTR2 CTS2 TXD2 RTS2 RXD2 DSR2 DCD2 L29 L30 L31 L32 L33 L34 L35 L36 BEAD BEAD BEAD BEAD BEAD BEAD BEAD BEAD 14 18 13 17 12 16 11 15 10 H3 H4 DCON9MX2 GGND B HEADER 10X2/BOX VCC VCC GPIO PORT 2/3 C47 MAX213 104 VCC 104 C48 1 2 3 4 5 6 7 8 9 10 11 12 13 14 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1C49 104 C50 104 T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RS485-2 J11 2-RS485+ 2-RS4851 2 3 HEADER 3-2.54mm/BOX VCC J12 External SPI FLASH VCC3 U9 R48 R49 SPICS SPIDO 1K Option A GP20 GP21 GP22 GP23 GP24 GP25 GP26 GP27 1 3 5 7 9 11 13 15 17 19 2 4 6 8 10 12 14 16 18 20 SPICS SPICLK SPIDO SPIDI GP34 GP35 GP36 GP37 DMP ELECTRONICS INC. VCC3 Title VORTEX86SX GPIO/COM/PWM 2MB SPI ROM Size Date: Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 3 2 A HEADER 10X2/BOX VCC3 VCC 1 2 3 4 CS# VCC SO HOLD# WP#/ACC SCLK GND SI 8 7 6 5 1K SPICLK SPIDI Rev 1.1 Sheet 1 5 of 8 5 4 5 4 3 2 1 U1I VORTEX86SX +1 +1 +1 +1 C51 VCC J13 2 2 2 1 2 HEADER 2-5.0mm 104 104 104 104 104 104 104 104 104 47uF 47uF 47uF 2 C52 C53 C54 C55 C56 C57 C58 C59 C60 C61 C62 C63 POWER CONNECTOR VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 VCC3 +1 VCC3 C64 2 47uF VCC3 +1 C65 2 47uF VCC1.8 + +1 +1 +1 C66 2 C67 104 104 104 104 104 104 104 104 47uF C68 C69 C70 C71 C72 C73 C74 C75 C76 2 47uF C77 2 47uF 47uF D +1 +1 2 2 VCC 3.3V 104 VCC U10 AIC1086-SOT223 VCC VIN VOUT VOUT ADJ R50 200 1% 104 104 104 104 104 104 104 3 VCC3 2 4 C81 C82 C83 C84 C85 C86 C87 C88 104 C89 104 VCC VCC VCC VCC VCC VCC VCC VCC +1 47uF 47uF VCC C90 2 47uF VCC +1 C91 2 47uF VCC +1 C92 2 47uF VCC +1 C93 2 47uF VCC +1 C94 2 47uF VCC +1 C95 2 47uF Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io Vss_io P17 P18 R11 R12 R15 R16 R17 R18 T9 T10 T13 T14 T15 U9 U17 V9 V17 W5 W6 AB21 AB22 AB23 AC20 1 1 V12 V11 V4 U16 U15 U14 U13 U12 U11 T18 T17 T16 AB4 AB5 AB6 AC10 AC11 AC12 C96 + 104 2 1 104 ADJ OUT IN 104 104 104 2 3 C100 104 C101 C102 C103 C104 SOT223 47uF 104 R51 330 1% +1 C97 1 C98 C99 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 VCC1.2 +1 +1 +1 C105 2 47uF C106 2 47uF C107 2 47uF C108 2 47uF + 47uF 2 Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core Vss_core C 2 +1 T11 T12 U10 V10 AA21 AA22 AA23 AC4 AC5 AC6 Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core Vdd_core VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 VCC1.8 C78 C79 C80 47uF D C U1H BYPASS VORTEX86SX VCC3 0.8*(1+150K/121K)=1.791735V VCC R2 VCC U11 LTC3701 SENSE+ VIN PGATE1 PGND PGATE2 PGOOD 7 8 R2 R61 78.7K/1% PLLLPF SENSE2EXTCLK SENSE2+ 16 15 14 13 12 11 VFB2 10 9 0.03/1206 R60 4 R58 0 3 R56 0.03/1206 0 3 1 SENSE1VFB1 ITH1 SGND ITH2 1 C109 3 R55 2 4 C113 220pF 6 5 10K 10K R57 VCC R1 1 C116 + R59 150K/1% C112 220pF + R1 R54 121K/1% R52 150K/1% R53 VCC1.8 L37 C 1 4.7uH/07x07 D3 1N5820 AA C110 + 47uF 2 2 VCC1.8 1 C111 + 47uF B E18 F18 J15 K15 L15 M15 M16 P10 P11 P12 P13 P14 VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC3V VCC 1.8V Q2 FDC638P 6 4 5 2 1 VCC3 47uF 2 B GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK GNDK E7 E8 E17 J10 J11 J12 K9 K10 K11 K12 L9 L10 L11 L12 M9 M10 M11 2 VCC1.2 1+ 47uF C L38 4.7uH/07x07 Q3 FDC638P VCC1.2 1 1 2 5 6 2 D4 1N5820 C114 C115 + 47uF 47uF 2 N17 N18 P15 P16 R9 R10 R13 R14 V3 W3 W4 AA4 AA5 AA6 AC21 AC22 AC23 Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io Vdd_io GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 GND_R3 N16 N15 N13 N12 N11 N10 N14 M13 M12 L13 K13 VCC1.2 VCC 1.2V 0.8*(1+78.7K/150K)=1.2197V R62 0 PWRGD 4 GND_R3 GND_R3 GND_R3 GND_R3 J13 F17 F16 F15 A F8 F13 F14 J14 K14 L14 M14 N9 P9 G4 VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK VCCK DMP ELECTRONICS INC. Title VORTEX86SX POWER Size Date: 4 3 2 A VCC3 F23 VCC_SPI D21 GND_SPI Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 Sheet 1 Rev 1.1 6 of 8 5 5 4 3 2 1 PRINT1/COM3/COM4 RI3 DTR3 CTS3 TXD3 RTS3 RS232 COM3 J14 DCD3 TXD3 RXD3 VCC HEADER 5X2/BOX DSR3 RTS3 RI3 1 3 5 7 9 2 4 6 8 10 RXD3 DTR3 DSR3 CTS3 RN23 22x4 1 1 1 1 1 1 1 1 PPD4 PPD5 PPD6 PPD7 PSLINPPD3 PPD2 PINITRN21 1 3 5 7 7 5 3 1 PD4 PD5 PD6 PD7 SLINPD3 PD2 INIT22x4 2 4 6 8 8 6 4 2 RN22 1 3 5 7 7 5 3 1 D 1Kx4 2 4 6 8 8 6 4 2 D DCD3\ RTS3\ DSR3\ RXD3\ C117 C118 C119 C120 C121 C122 C123 C124 RN24 1Kx4 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF 1 1 1 1 1 1 1 1 RXD3\ TXD3\ RTS3\ DCD3\ CTS3\ RI3\ DTR3\ DSR3\ RXD3\ TXD3\ RTS3\ DCD3\ CTS3\ RI3\ DTR3\ DSR3\ U12 CTS3\ TXD3\ DTR3\ RI3\ DCD3 VCC C125 1 PERRORERR104 104 C126 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1 1 1 1 1 1 1 1 R63 22 PPD1 PPD0 PAFDPSTBPSLCT PPE PBUSY PACKRN25 7 5 3 1 7 5 3 1 RN27 PD1 PD0 AFDSTBSLCT PE BUSY ACK22x4 8 6 4 2 8 6 4 2 22x4 C127 C128 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 RN26 1Kx4 7 8 5 6 3 4 1 2 7 8 5 6 3 4 1 2 RN28 1Kx4 R64 1K C129 C130 C131 C132 C133 C134 C135 C136 C137 D5 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF 181pF 1N4148 VCC C MAX213 104 104 C VCC J15 SLCT PE BUSY RI4 DTR4 CTS4 TXD4 RTS4 RS232 COM4 J16 DCD4 TXD4 RXD4 VCC DSR4 HEADER 5X2/BOX RTS4 RI4 1 3 5 7 9 2 4 6 8 10 RXD4 DTR4 DSR4 CTS4 ACKPD7 PD6 PD5 PD4 DCD4\ RTS4\ DSR4\ RXD4\ B B 1 1 1 1 1 1 1 1 RXD4\ TXD4\ RTS4\ DCD4\ CTS4\ RI4\ DTR4\ DSR4\ RXD4\ TXD4\ RTS4\ DCD4\ CTS4\ RI4\ DTR4\ DSR4\ U13 PRINT1 CTS4\ TXD4\ DTR4\ RI4\ DCD4 VCC C138 104 104 C139 1 2 3 4 5 6 7 8 9 10 11 12 13 14 C140 C141 T3OUT T1OUT T2OUT R2IN R2OUT T2IN T1IN R1OUT R1IN GND VCC C1+ V+ C1- T4OUT R3IN R3OUT SHDN /EN R4IN R4OUT T4IN T3IN R5OUT R5IN VC2C2+ 28 27 26 25 24 23 22 21 20 19 18 17 16 15 PD3 SLINPD2 INITPD1 ERRPD0 AFDSTB- 13 25 12 24 11 23 10 22 9 21 8 20 7 19 6 18 5 17 4 16 3 15 2 14 1 DB25A 28 27 26 MAX213 GGND 104 104 VCC A A DMP ELECTRONICS INC. Title VORTEX86SX PRN1/COM3/4 Size Date: 4 3 2 Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 Sheet 1 Rev 1.1 7 of 8 5 5 4 3 2 1 PC-104 / Full 16Bit ISA BUS VCC VCC J17 -12V IOCHCK 2 VCC3 VCC3 INT-A INT-C +12V PCI SLOT D J18 D 2 2 2 SD[0..15] SD[0..15] 2 2 PCICLK1 CBE-0 CBE-1 CBE-2 CBE-3 PREQ-0 AD31 AD29 AD27 AD25 CBE-3 AD23 PCIRSTAD17 CBE-2 IRDYDEVSELPLOCKPERRSERRCBE-1 AD14 AD12 AD10 2 2 2 2 INT-A INT-B INT-C INT-D INT-A INT-B INT-C INT-D AD21 AD19 PCICLK1 2 PGNT-0 PGNT-0 2 IOCHRDY AEN PREQ-0 PREQ-0 AD[0..31] AD[0..31] INT-B INT-D RSTDRV PCI BUS 2 IRQ9 2 DRQ2 2 RSTDRV VCC IRQ9 -5V DRQ2 -12V OWS +12V OWS VCC3 PCIRSTPGNT-0 AD30 AD28 AD26 AD24 AD12 AD22 AD20 AD18 AD16 FRAMETRDYSTOPC 2 2 2 2 2 PCICLK1 CBE-0 CBE-1 CBE-2 CBE-3 C 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 PCIRST- SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE 2 SA[0..19] SA[0..19] 2 SMEMW SMEMR IOW IOR DACK3 DRQ3 DACK1 DRQ1 REFRESH SYSCLK IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 DACK2 TC BALE VCC OSC FRAMEIRDYTRDYDEVSELSTOPPAR OSC 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 52 54 56 58 60 62 64 2 2 2 2 2 2 FRAMEIRDYTRDYDEVSELSTOPPAR 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 51 53 55 57 59 61 63 IOCHCK SD7 SD6 SD5 SD4 SD3 SD2 SD1 SD0 IOCHRDY AEN SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10 SA9 SA8 SA7 SA6 SA5 SA4 SA3 SA2 SA1 SA0 HEADER 32X2 J19 PAR AD15 AD13 AD11 AD9 B SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW 2 2 2 2 2 2 2 2 2 2 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 B21 B22 B23 B24 B25 B26 B27 B28 B29 B30 B31 B32 B33 B34 B35 B36 B37 B38 B39 B40 B41 B42 B43 B44 B45 B46 B47 B48 B49 -12V TCK GND TDO +5V +5V INTB INTD PRSNT1 RESERVED1 PRSNT2 GND GND RESERVED2 GND CLK GND REQ +5V AD31 AD29 GND AD27 AD25 +3.3V C/BE3 AD23 GND AD21 AD19 +3.3V AD17 C/BE2 GND IRDY +3.3V DEVSEL GND LOCK PERR +3.3V SERR +3.3V C/BE1 AD14 GND AD12 AD10 GND TRST +12V TMS TDI +5V INTA INTC +5V RESERVED3 +5V RESERVED4 GND GND 3.3V_AUX RST +5V GNT GND PME AD30 +3.3V AD28 AD26 GND AD24 IDSEL +3.3V AD22 AD20 GND AD18 AD16 +3.3V FRAME GND TRDY GND STOP +3.3V SDONE SBO GND PAR AD15 +3.3V AD13 AD11 GND AD9 AD8 AD7 AD5 AD3 AD1 VCC R66 4.7K CBE-0 AD6 AD4 AD2 AD0 R67 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 A22 A23 A24 A25 A26 A27 A28 A29 A30 A31 A32 A33 A34 A35 A36 A37 A38 A39 A40 A41 A42 A43 A44 A45 A46 A47 A48 A49 B 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 VCC MEMCS16 IOCS16 IRQ10 IRQ11 IRQ12 IRQ15 IRQ14 DACK0 DRQ0 DACK5 DRQ5 DACK6 DRQ6 DACK7 DRQ7 MASTER R65 SD[0..15] SD[0..15] 2 SBHE LA23 LA22 LA21 LA20 LA19 LA18 LA17 MEMR MEMW SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 4.7K VCC 4.7K HEADER 20X2 B52 B53 B54 B55 B56 B57 B58 B59 B60 B61 B62 AD8 AD7 +3.3V AD5 AD3 GND AD1 +5V ACK64 +5V +5V PCI-5V_SLOT_120P C/BE0 +3.3V AD6 AD4 GND AD2 AD0 +5V REQ64 +5V +5V A52 A53 A54 A55 A56 A57 A58 A59 A60 A61 A62 VCC -5V VCC +12V -12V VCC A C142 C143 C144 SMEMW SMEMR IOW IOR VCC RN30 1 3 5 7 4.7K 2 4 6 8 VCC3 VCC3 VCC3 R68 R69 R72 4.7K 4.7K 4.7K PLOCKPERRSERR- A DMP ELECTRONICS INC. Title VORTEX86SX PC104/PCI SLOT Size Date: Document Number VORTEX86SX SOC Reference Design Monday, January 29, 2007 3 2 104 104 104 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 IOCHRDY MEMCS16 IOCS16 R70 R71 R73 330 330 330 RN29 1 3 5 7 1 3 5 7 RN31 4.7K 2 4 6 8 2 4 6 8 4.7K Rev 1.1 Sheet 1 8 of 8 5 4 |
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